He has published more than 120 research papers in referred conferences and journals. He is actively participating in professional activities. He has been served as an editor for several journals such as IEEE Transactions on Signal Processing. In 1994, He served as the Program Committee Chair for the Fourth IEEE Great Lakes Symposium on VLSI. He also served as program committee in numerous conferences such as International Symposium on System Synthesis, International Conference on Parallel and Distributed Computing and Systems, and International Symposium on the Frontiers of Massively Parallel Computation, etc. He received Oak Ridge Association Junior Faculty Enhancement Award in 1994, and NSF CAREER Award in 1995 in the area of Design, Tools and Test. He was a guest editor for the special issue on Low Power Design of IEEE Transactions on VLSI Systems in 1997. He is also serving as the program chair for the International Conference on Parallel and Distributed Computing Systems, 2000 and 2001.

His research interests include computer architectures, system-level synthesis, embedded systems, networking, parallel and distributed systems, operating systems, compilers, and multimedia systems. He has published more than 120 papers and graduated 5 Ph.D. students in the past 7 years. Currently he is advising 7 Ph.D. students. He received Undergraduate Teaching Award in 1998.

Recently he has been developing new techniques that combine optimal partitioning, loop pipelining and intelligent prefetching to hide data accesses. He is also studying various off-line and on-line page replacement algorithms for deep memory hierarchy. His research on time-and-memory optimization for computation intensive and communication intensive applications has produced significant results, which solved several important problems. Several optimization algorithms have been developed such as MD retiming, MD rotation, MD interleaving, communication-sensitive scheduling, and carrot-hole data scheduling and partitioning. He is also investigating design optimization techniques for applications with conditional branches, low-power requirement, and fuzzy or probabilistic uncertainty. New techniques such as branch anticipation, low-power scheduling, probabilistic retiming, probabilistic loop pipelining, and WIZARD design space exploration were recently developed. The detailed information can be found on the web at http://www.nd.edu/~esha.

Research Interests

Parallel Architectures and Systems, Embedded Systems, Memory Issues, Parallel Compiler, Scheduling and Partitioning, Multimedia Systems, CAD Algorithms, VLSI Signal Processing, Operating Systems, Distributed Systems, High-Level Synthesis.

Citizenship:

USA

Education

Ph.D. Computer Science	Princeton University	Oct. 1992
Thesis title: Real-Time Fault Tolerance for Array Architectures
Advisor: Prof. Kenneth Steiglitz
M.A. Computer Science	Princeton University	Jan. 1991
B.S.E. Computer Science	National Taiwan University	June 1986
(GPA: 3.9/4.0, Book Coupon Awards, five times)

Professional Experience

Aug. 00 - Present	Professor (Tenured)	Dept. of Computer Science
		University of Texas at Dallas, TX
Aug. 98 - Aug. 00	Associate Professor (Tenured)	Dept. of Computer Science & Engr.
	Associate Chairman	University of Notre Dame, IN
May 95 - Aug. 98	Assistant Professor	Dept. of Computer Science & Engr.
	Associate Chairman	University of Notre Dame, IN
Aug. 92 - May 95	Assistant Professor	Dept. of Computer Science & Engr.
		University of Notre Dame, IN
Sep. 88- July 92	RA and TA	Dept. of Computer Science
		Princeton University, NJ
Aug. 86- May 88	System Programmer	Marine Corps, Taiwan

Membership

ACM and The Institute of Electrical and Electronics Engineers (Computer Society, Signal Processing Society, and Circuits and Systems Society).

Courses taught and designed since August 1992

Data Structures, VLSI Processor Arrays, Principles of Parallel Computing, Specialized Parallel Architectures, Operating Systems Principles, Automata.

Graduate Students Advised (as their major research advisor)

1. Joy Chantrapornchai, Ph.D. degree, 1999, Ph.D. Dissertation Title: System Level Synthesis Considering Impreciseness Based on Fuzzy Theory.

2. Sissadas Tongsima, Ph.D. degree, 1999, Ph.D. Dissertation Title: Loop Scheduling for Applications with Fixed or Probabilistic Timing Information.

3. Milind Saraph, Master degree, 1998, Thesis Title: Distributed File Systems: An Emprical Study.

4. David Surma, Ph.D. degree, 1998, Ph.D. Dissertation Title: Collision Graph Based Communication Scheduling and Applications.

5. Kaisheng Wang, Master Degree, 1998, Thesis Title: Register Constrained Rotation Scheduling.

6. Ted Zhihong Yu, Master Degree, 1997, Thesis Title: Algorithms and Hardware Support for Multi-Dimensional Branch Anticipation.

7. Michael Sheliga, Ph.D. Degree, 1997, Ph.D. Dissertation Title: Efficient High Level synthesis Using Hardware/Multi-Software Co-Design and Communication Minimization.

8. Nelson Passos, Ph.D. Degree, 1996, Ph.D. Dissertation Title: The Multi-Dimensional Retiming Framework.

9. Nicole Sabine, Master Degree, 1995, Thesis Title: Selectively Fault-Tolerant, Hard Real-Time Multiprocessor Scheduling.
10. Yvonne (YuHong) Wang, Master Degree, 1995, Thesis Title: Scheduling via Node Replication for Parallel Systems.
11. Sissadas Tongsima, Master Degree, 1995, Thesis Title: Communication Sensitive Scheduling for Parallel systems.
12. Jenny (QingYan) Wang, Master Degree, 1995, Thesis Title: Memory Constrained Partitioning and Scheduling for Multi-dimensional Applications.
13. John Swadener, Master Degree, 1994, Thesis Title: A Simulation Environment for Automatic Partitioning and Scheduling of Parallel Programs Based on Simulated Annealing.

Undergraduate Students Advised

1. Roger Patrick Gorman and Ronald Setia, 1999 and 2000, Research Project: Java Parallel Virtual Machines.
2. Sam Ruppert and Richard Wiseman, 1999 and 2000, Research Project: Virtual Network Chat with Animated Face.
3. Melissa Layton, Vincent Oh, 1999 and 2000, Research Project: Virtial Mobile Dog: An exmaple of Mobile Agent.
4. Ronald Setia, Mohamed Helmy, and Roger Gorman, 1999, Research Project: Simulator for Java Virtual Machine and Pipelined JVM.

5. Ryan Carlson and Michael Dreznes, 1998 and 1999, Research Project: Java Virtual Conference.

6. Dominic Fahey and Clinton Grady,1998 and 1999, Research Project: Multiple-thread Real-Time Java Based Web Camera.

7. Joseph Bishay and Donald Reinhart, 1997, Research Project: Pegasus: tools for collaborating and communicating for multiple users.

8. Nathan Isley, CSE, 1997, Research Project: Virtual Friend based on Java.

9. Becky Saydak, CSE, 1995, Research Project: Real-Time Multiprocessor Scheduling for Fault-tolerance.

10. Thomas Aranda, CSE, 1995, Research Project: Simulation Tools for Parallel Systems.

11. Dan Cieslak, CSE, 1995 and 1996, Research Project: Efficient Parallel Programming.

Graduate Students being Advised

1. Michael Kirkpatrick, Ph.D. Student, Research Project: System-level Synthesis for Low Power.

2. Timothy O'Neil, Ph.D. Student, Research Project: Optimal Scheduling using New Graph Transformation Algorithms: Extended Retiming.

3. Fei Chen, Ph.D. Student, Research Project: Intelligent Prefetching Algorithms.
4. JiangFeng Ding, Ph.D. Student, Research Project: Probabilistic Evaluation of QoS for Real-time Network.

5. Zhong Wang, Ph.D. Student, Research Project: Optimal Data Partitioning and Loop Scheduling for DSP Applications.

6. Virgil Andronache, Ph.D. Student, Research Project: Intelligent Page Placement and Replacement on Multiple Level Memory Systems.

7. Jon Furgeson, Ph.D. Student, Research Project: Efficient Searching for Multimedia Time Domain Based Information.

Grants

• Oak Ridge Associated Universities, Timing Optimization for Multi-Dimensional Scientific Applications, Principal Investigator, $10,000, June 1994 - May 1995.

• NSF Cornell Theory Center, 90 service units for KSR and IBM SP1, Principal Investigator, August 1993 - January 1994.

• NSF CAREER Award, High-Level Design Methodologies for Time-Optimal and Memory-Optimal Systems, Principal Investigator, MIPS 95-01006, $139,000, (the amount from NSF), June 1995 - May 1998.

• NSF Pittsburgh Supercomputing Center, 554 Service Units for Cray C90 and Cray T3D, Principal Investigator, September 1995 - September 1996.

• NSF National Center for Supercomputing Applications, 25 SU Hours for CM5, Principal Investigator, August 1995 - January 1996.

• NSF Cornell Theory Center, 100 service units for IBM SP2, Principal Investigator, August 1995 - January 1996.

• NSF Equipment Grant, Principal Investigator, MIPS 95-01006, $50,000, May 1996 - May 1998.

• NSF, Co-PI (with Peter Kogge, Jay Brockman, Steven Bass, and Danny Chen), Pursuing A Petaflop: Point Designs for 100 TF Computers Using PIM Technologies, NSF ACS 96-12028, $100,000, April 1996 - May 1997.

• NSF, Co-PI (with Nelson Passos), Architecture support and code generation for general nested loops with fine-grain parallelism, MIP-9704276, $240,000, July 1997 - June 2000.

• JPL (funded by DARPA, NSA and NASA), Co-PI (with Peter Kogge, Steven Bass, Jay Brockman, Andy Lumnsdaine and Vincent Freeh), A Hybrid Technology MultiThreaded Architecture for Petaflops Computing, JPL Award No. 961097, $604,000, May 1997 - June 1999.

• AT&T, PI, Communication Bandwidth Reduce Techniques & IP video Phone, Award No. A-98-11-00002, $25,000, May 1998 - August 1999.

• AT&T, PI, Video Chat and Bandwidth Reduction Techniques, $25,000, September 1999 - May 2001.

• NSF, PI, Optimal data scheduling, data placement and architectural support for multi-memory hierarchy, $422,520, June 2000 - May 2003, Submitted.

• NSF, Co-PI, New Synthesis Methodology and Optimization Targeting Transistor-level Design for Low Power DSP applications, $459,235, June 2000 - May 2003, Submitted.

• 21st CRTF Indiana, PI, New Techniques Based on Application-Specific Approaches to Increase Throughput in High-Performance Networks , $418,295, Jan. 2000 - Dec. 2001, Submitted.

Professional Activities and Awards

• Program Committee Co-Chair (with Prof. Ghulam M. Chaudhry) of the 13th ISCA International Conference on Parallel and Distributed Computing Systems (PDCS), Las Vegas, Nevada, August 2000.

• Editor, Journal of VLSI Signal Processing Systems, 2000 to 2003.

• Editor, IEEE Transactions on Signal Processing, handling submissions related to VLSI Systems and Programming Systems, 1999 to 2001.

• Faculty Undergraduate Teaching Award of the Department of Computer Science and Engineering, University of Notre Dame, 1998.

• Co-Guest editor (with Prof. Anantha Chandrakasanon at MIT) on low power VLSI systems, IEEE Transactions on VLSI Systems, published in Dec. 1998.

• Editor, Journal of Circuits, systems and Computers, 1998.

• NSF CAREER Award, High-Level Design Methodologies for Time-Optimal and Memory-Optimal Systems, 1995.

• 1994 Junior Faculty Enhancement Award of Oak Ridge Associated University in Mathematics/Computer Science.

• An Honorable alternate of 1993 Junior Faculty Enhancement Award of Oak Ridge Associated University in Mathematics/Computer Science.

• Associate Chairman of the Department of Computer Science and Engineering, University of Notre Dame, August 1995 - present.

• Graduate Committee of the Department of Computer Science and Engineering, University of Notre Dame, October 1992 - present.

• College Council, Engineering College, University of Notre Dame, August 1995 - May 1997.

• Honesty Committee of the Department of Computer Science and Engineering, University of Notre Dame, August 1994 - present.

• Program Committee of the 4th IEEE International Conference on Algorithms and Architecture for Parallel Processing (ICA3PP2000), Hong Kong, December 2000.

• Program Committee of the 11th International Conference on Parallel and Distributed Computing and Systems, Cambridge, MA, November, 1999.

• Program Committee of the IEEE Seventh International Symposium on the Frontiers of Massively Parallel Computation, Annapolis, Maryland, February, 1999.

• Program Committee of the IEEE/ACM 11th International Symposium on System Synthesis, Hsinchu, Taiwan, December, 1998.

• Program Committee of the 10th International Conference on Parallel and Distributed Computing and Systems, Las Vegas, Nevada, October, 1998.

• Program Committee of the IEEE/ACM 10th International Symposium on System Synthesis, Antwerp, Belgium, September, 1997.

• Program Committee of the IEEE Seventh Great Lakes Symposium on VLSI, Urbana, Illinois, March, 1997.

• Program Committee of the IEEE/ACM Ninth International Symposium on System Synthesis, La Jolla, California, November, 1996.

• Program Committee of the IEEE Sixth International Symposium on the Frontiers of Massively Parallel Computation, October, 1996.

• Program Committee of the IEEE Sixth Great Lakes Symposium on VLSI, Ames, Iowa, March, 1996.

• Program Committee of the IEEE Fifth Great Lakes Symposium on VLSI, Buffalo, New York, March, 1995.

• Program Committee Co-Chair (with Prof. John Uhran) of the IEEE Fourth Great Lakes Symposium on VLSI, March, 1994, Notre Dame, Indiana. (Co-sponsored by IEEE Computer society, and IEEE Circuits and Systems Society and in cooperation with ACM).

• Reviewer for Proposals submitted to NSF Microelectronic systems Architecture Program and Design, Tool and Test Program.

• Reviewer for many journals including IEEE Transactions on VLSI Systems, IEEE Transactions on CAD, Journal of VLSI Signal Processing, IEEE Transactions on Circuits and Systems, IEEE Transactions on Parallel and Distributed Systems, IEEE Transactions on Signal Processing, etc.

Refereed Publications

Regular Journal Papers Published or Accepted for Publication

1. D. R. Surma, E. H.-M. Sha and P. M. Kogge, ``Communication Reduction in Multiple Multicasts based on Hybrid Static-Dynamic Scheduling," Accepted for Publication in IEEE Transactions on Parallel and Distributed Systems.

2. C. Chantrapornchai, E. H.-M. Sha, and X. Sharon Hu, ``Efficient Acceptable Design Exploration Based on Module Utility Selection," in IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol 19, No. 1, Jan. 2000, pp. 19-29.

3. F. Chen, T. W. O'Neil, and E. H.-M. Sha, ``Optimizing Overall Loop Schedules using Prefetching and Partitioning,'' in IEEE Transactions on Parallel and Distributed Systems, Vol. 11, No. 6, June 2000.

4. S. Tongsima, E. H.-M. Sha, C. Chantrapornchai, D. Surma and N. Passos, ``Probabilistic Loop Scheduling for Applications with Uncertain Execution Time," in IEEE Transactions on Computers, Vol. 49, No. 1, Jan. 2000, pp. 65-80.

5. S. Tongsima, T. W. O'Neil, C. Chantrapornchai and E. H.-M. Sha, ``Properties and Algorithms for Unfolding of Probabilistic Data-flow Graphs," in Journal of VLSI Signal Processing, Vol. 25, No. 3, July 2000, pp. 215-234.

6. C. Chantrapornchai, E. H.-M. Sha, and X. Sharon Hu, ``Efficient Module Selections for Finding Highly Acceptable Designs based on Inclusion Scheduling,'' Accepted for publication in Journal of Systems Architecture.

7. E. H.-M. Sha, and C. Chantrapornchai, ``Optimizing Page Replacement for Multiple-Level Memory Hierarchy," (regular paper) in International Journal of Computers and Their Applications, Vol. 6, No. 4, Dec. 1999, pp. 212-222.

8. N. Passos and E. H.-M. Sha, ``Scheduling of Uniform Multi-Dimensional Systems under Resource Constraints," (regular paper) in IEEE Transactions on VLSI Systems, Vol. 6, No. 4, December 1998, pp. 719-730.

9. S. Tongsima, E. H.-M. Sha, C. Chantrapornchai, and N. Passos, ``Efficient Loop Scheduling and Pipelining for Applications with Non-uniform Loops," (regular paper) in IASTED International Journal of Parallel and Distributed Systems and Networks, Vol. 1, No 4, 1998, pp. 204-211.

10. L.-F. Chao and E. H.-M. Sha, ``Scheduling Data-Flow Graphs via Retiming and Unfolding," (regular paper) in IEEE Transactions on Parallel and Distributed Systems, Vol. 8, No. 12, December 1997, pp. 1259-1267.

11. S. Tongsima, C. Chantrapornchai, E. H.-M. Sha and N. Passos, ``Reducing Data Hazards on Multi-pipelined DSP Architecture with Loop Scheduling," (regular paper) in Journal of VLSI Signal Processing, Vol. 18, 1998, pp. 111-123.

12. D. R. Surma and E. H.-M. Sha, ``Collision Graph based Communication Scheduling for Parallel Systems," (regular paper) in International Journal of Computers and Their Applications. Vol. 5, No. 1, March 1998, pp. 11-22.

13. Q. Wang, E. H.-M. Sha and N. Passos, ``Minimization of Memory Access Overhead for Multi-dimensional DSP Applications via Multi-level Partitioning and Scheduling," (regular paper) in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 44, No. 9, September 1997, pp. 741-753.

14. S. Tongsima, E. H.-M. Sha and N. Passos, ``Communication Sensitive Loop Scheduling for DSP Applications," (regular paper) in IEEE Transactions on Signal Processing, Vol. 45, No. 5, May 1997, pp. 1309-1322.

15. L.-F. Chao, E. H.-M. Sha and A. LaPaugh, `` Rotation Scheduling: A Loop Pipelining Algorithm,'' (regular paper) in IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 16, No. 3, March 1997, pp. 229-239.

16. N. Passos, E. H.-M. Sha and L.-F. Chao, ``Multi-Dimensional Interleaving for Synchronous Circuit Design Optimization," (regular paper) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16, No. 2, February 1997, pp. 146-159.

17. N. Passos and E. H.-M. Sha, ``Achieving Full Parallelism using Multi-Dimensional Retiming," (regular paper) in IEEE Transactions on Parallel and Distributed Systems, Vol. 7, No. 11, November 1996, pp. 1150-1163.

18. M. Sheliga and E. H.-M. Sha, ``Hardware/Software Co-design With the HMS Framework," (regular paper) in Journal of VLSI Signal Processing Systems, Vol. 13, No. 1, August 1996, pp. 37-56.

19. N. Passos and E. H.-M. Sha, ``Synchronous Circuit Optimization via Multi-Dimensional Retiming," (regular paper) in IEEE Transactions on Circuits and Systems, vol II - Analog and Signal Processing, Vol. 43, No. 7, July 1996, pp. 507-519.

20. L.-F. Chao and E. H.-M. Sha, ``Static Scheduling for Synthesis of DSP Algorithms on Various Models," (regular paper) in Journal of VLSI Signal Processing, Vol 10, 1995, pp 207-223.

21. E. H.-M. Sha and K. Steiglitz, ``Maintaining Bipartite Matchings in the Presence of Failures,'' (regular paper) in Networks Journal, Vol. 23, No. 5, August 1993, pp. 459-471.

22. E. H.-M. Sha and K. Steiglitz, ``Reconfigurability and Reliability of Systolic/Wavefront Arrays,'' (regular paper) in IEEE Transactions on Computers, Vol. 42, No. 7, July 1993, pp. 854-862.

23. E. H.-M. Sha and K. Steiglitz, ``Error Detection in Arrays via Dependency Graphs,'' (regular paper) in Journal of VLSI Signal Processing, Vol. 4, No. 4, October 1992, pp 331-342.

    Published Short Journal Papers

24. Q. Wang, E. H.-M. Sha and N. Passos, ``Optimal Data Scheduling for Uniform Multi-dimensional Applications," IEEE Transactions on Computers, Vol. 45, No. 12, December 1996, pp. 1439-1444.

25. N. Passos, E. H.-M. Sha and S. C. Bass, ``Optimizing DSP Flow Graphs via Schedule-Based Multi-Dimensional Retiming," IEEE Transactions on Signal Processing, Vol. 44, No. 1, January, 1996, pp. 150-156.

    Submitted Journal Papers Waiting for Review Decision

26. Z. Wang, T. W. O'Neil and E. H.-M. Sha, ``Optimal Loop Scheduling for Hiding Memory Latency Based on Two Level Partitioning and Prefetching," submitted to IEEE Transactions on Signal Processing.

27. T. W. O'Neil, and E. H.-M. Sha, ``Combining Extended Retiming and Unfolding for Rate-Optimal Graph Transformation," submitted to IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing.

28. X. Hu, T. Zhou and E. H.-M. Sha, ``Estimating Probabilistic Timing Performance for Real-time Embedded systems," submitted to IEEE Transactions on VLSI Systems.

29. T. W. O'Neil, S. Tongsima, and E. H.-M. Sha, ``Extended Retiming: A Graph Transformation Technique for Optimal Scheduling of Data-Flow Graphs," submitted to IEEE Transactions on Parallel and Distributed Systems.

30. V. Andronache, E. H.-M. Sha and N. L. Passos ``Generalized Off-line Algorithm and Related On-line Algorithms for Multi-level Memory Hierarchies," submitted to IEEE Transactions on Computers.

31. E. H.-M. Sha and N. Passos, ``Algorithms and Architecture Support for Pipelining and Scheduling Nested Loops with Conditions," submitted to Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology.

32. M. Sheliga, N. Passos and E. H.-M. Sha, ``A Fully Parallel Design Methodology for Multi-Dimensional DSP Applications," submitted to Journal of VLSI Signal Processing.

33. E. H.-M. Sha, T. W. O'Neil and N. Passos, ``Efficient Polynomial-time Nested Loop Fusion with Full Parallelism," submitted to International Journal of Computers and Their Applications.

34. Z. Wang, T. W. O'Neil and E. H.-M. Sha, ``Minimizing Average Schedule Length under Memory Constraints by Optimal Partitioning and Prefetching," submitted to Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology.

35. C. Chantrapornchai, S. Tongsima and E. H.-M. Sha, "Rapid Prototyping Implementation and Optimization based on Conceptual Specification for Fuzzy Applications," submitted to Journal of Fuzzy Sets and Systems.

36. D. Surma, E. H.-M. Sha and N. Passos, ``Communication Scheduling with Re-routing based on Static and Hybrid Techniques," submitted to Journal of Circuits, Systems and Computers.

    
    
    

    Referred Conference Papers

37. R. Light, W. Maxfield, B. Reed, N. L. Passos, and E. H.-M. Sha, ``Improving Nested Loops' ILP on a Parallel ASIC Design," to appear in ISCA 13th International Conference on Parallel and Distributed Computing Systems, Las Vegas, Nevada, August, 2000.

38. T. O'Neil and E. H.-M. Sha, ``Minimizing Inter-Iteration Dependencies for Loop Pipelining," to appear in ISCA 13th International Conference on Parallel and Distributed Computing Systems, Las Vegas, Nevada, August, 2000.

39. Z. Wang, M. Kirkpatrick, and E. H.-M. Sha, ``Optimal Two Level Partitioning and Loop Scheduling for Hiding Memory Latency for DSP Applications," to appear in Proc. ACM 37th Design Automation Conference, Los Angeles, California, June, 2000, pp. 450-455.

40. J. Ding, J. C. Furgeson and Edwin H..-M. Sha, ``Application Specific Image Compression for Virtual Conferencing," in Proc. IEEE International Conference on Information Technology: Coding and Computing, Las Vegas, Nevada, March 2000, pp. 48-53.

41. C. Chantrapornchai, E. H.-M. Sha and S. X. Hu, ``Efficient Algorithms for Acceptable Design Exploration," in Proc. IEEE Tenth Great Lakes Symposium on VLSI, Evanston, Illinois, March, 2000, pp. 139-142.

42. V. Andronache, E. H.-M. Sha and N. Passos, ``Design and Analysis of Efficient Application-Specific On-line Page Replacement Techniques," in Proc. IEEE Tenth Great Lakes Symposium on VLSI, Evanston, Illinois, March, 2000, pp. 123-128.

43. J. Ding, M. Kirkpatrick, and E. H.-M. Sha, ``QoS Measures and Implementations Based on Various Models for Real-time Communications," in 3rd IEEE Symposium on Application-Specific Systems and Software Engineering Technology, Richardson, Texas, March, 2000, pp 106-110.

44. T. W. O'Neil, and Edwin H.-M. Sha, ``Rate-Optimal Graph Transformation Based on Extended Retiming and Unfolding," in Proc. 11th IASTED International Conference on Parallel and Distributed Computing and Systems, Cambridge, MA, November 1999, pp. 764-769.

45. Z. Wang, V. Andronache, and Edwin H.-M. Sha , ``Optimal Partitioning under Memory Constraints for Minimizing Average Schedule Length," in Proc. 11th IASTED International Conference on Parallel and Distributed Computing and Systems, Cambridge, MA, November 1999, pp. 758-763.

46. F. Chen, and E. H.-M. Sha, ``Loop Scheduling and Partitions for Hiding Memory Latencies," in Proc. IEEE 12th International Symposium on System Synthesis, San Jose, CA, November 1999, pp. 64-70.

47. T. O'Neil, S. Tongsima, and E. H.-M. Sha, ``Optimal Scheduling of Data-Flow Graphs Using Extended Retiming," in Proc. ISCA 12th International Conference on Parallel and Distributed Computing Systems, Fort Lauderdale, Florida, August, 1999.

48. N. L. Passos, R. Light, V. Andronache, E. H.-M. Sha, ``Design of 2-D Filters using a Parallel Processor Architecture," in Proc. ISCA 12th International Conference on Parallel and Distributed Computing Systems, Fort Lauderdale, Florida, August, 1999.

49. T. O'Neil, S. Tongsima, and and E. H.-M. Sha, ``Extended Retiming: Optimal Scheduling via a Graph-Theoretical Approach," in Proc. 1999 IEEE International Conference On Acoustics, Speech, and Signal Processing, Phoenix, Arizona, March 1999, Vol. 4, pp. 2001-2004.

50. S. Tongsima, T. O'Neil, and E. H.-M. Sha, ``Unfolding Probabilistic Data-flow Graphs Under Different Timing Models," in Proc. 1999 IEEE International Conference On Acoustics, Speech, and Signal Processing, Phoenix, Arizona, March 1999, Vol 4, pp. 1889-1892.

51. T. Zhou, X. S. Hu and Edwin H.-M. Sha, ``A Probabilistic Performance Metric for Real-Time System Design ," in Proc. 1999 7th International Workshop on Hardware Software Co-Design, Rome, Italy, May 1999, pp. 90-94.

52. T. Zhou, X. S. Hu and Edwin H.-M. Sha, ``Probabilistic Performance Estimation for Real-time Embedded Systems," in Proc. 1999 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, March, 1999, pp. 83-88.

53. C. Chantrapornchai, E. H.-M. Sha, and X. S. Hu, ``Efficient Algorithms for Finding Highly Acceptable Designs Based on Module-Utility Selections," in Proc. IEEE 9th Great Lakes Symposium on VLSI, Ann Arbor, Michigan, March, 1999, pp. 128-131.

54. Y. Tian, E. H.-M. Sha, C. Chantrapornchai, and P. M. Kogge, ``Efficient Data Placement and Replacement Algorithms for Multiple-Level Memory Hierarchy," in Proc. 10th International Conference on Parallel and Distributed Computing and Systems, Las Vegas, Nevada, October, 1998, pp. 196-201.

55. F. Chen, S. Tongsima, and E. H.-M. Sha, ``Loop Scheduling Optimization with Data Prefetching based on Multi-dimensional Retiming," in Porc. ISCA 11th International Conference on Parallel and Distributed Computing Systems, Chicago, Illinois, September, 1998, pp. 129-134.

56. D. R. Surma, E. H.-M. Sha and P. M. Kogge, ``Communication Reduction Techniques for Multiple Multicasts based on Collision Graphs," in Porc. ISCA 11th International Conference on Parallel and Distributed Computing Systems, Chicago, Illinois, September, 1998, pp. 93-98.

57. F. Chen, S. Tongsima, and E. H.-M. Sha, ``Loop Scheduling Algorithm for Timing and Memory Operation Minimization with Register Constraint,'' in Proc. 1998 IEEE Workshop on SIGNAL PROCESSING SYSTEMS (SiPS), Boston, Massachusetts, October, 1998, pp. 579-588.

58. Andrea Leonardi, Nelson L. Passos, and Edwin H.-M. Sha, ``Nested Loops Optimization for Multiprocessor Architecture Design", in Proc. 1998 Midwest Symposium on Circuit and Systems, Notre Dame, Indiana, August, 1998.

59. C. Chantrapornchai, E. H.-M. Sha and S. X. Hu, ``Efficient Scheduling for Imprecise Timing Based on Fuzzy Theory," in Proc. 1998 Midwest Symposium on Circuit and Systems, Notre Dame, Indiana, August, 1998, pp. 272-275.

60. S. Tongsima, C. Chantrapornchai, E. H.-M. Sha and N. Passos `` Optimizing Circuits with Confidence Probability using Probabilistic Retiming," in Proc. IEEE International Conference on Circuits and Systems, Monterey, California, June, 1998.

61. D. R. Surma, E. H.-M. Sha and P. M. Kogge, ``Compile-time Priority Assignment and Re-routing for Communication Minimization in Parallel Systems," in Proc. IEEE International Conference on Circuits and Systems, Monterey, California, June, 1998.

62. M. Sheliga, T. Yu, F. Chen, and E. H.-M. Sha, ``Graph Transformation for Communicaton Minimization Using Retiming," in Proc. IEEE International Conference on Circuits and Systems, Monterey, California, June, 1998.

63. T. Z. Yu, F. Chen and E. H.-M. Sha, ``Loop Scheduling Algorithms for Power Reduction," in Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, Seattle, Washington, May 1998, Vol. 5, pp. 3073-3076.

64. C. Chantrapornchai, S. Tongsima, E. H.-M. Sha and S. X. Hu, ``Dealing with Impreciseness in Architectural Synthesis," in Proc. IASTED International Conference on Artificial Intelligence and Soft Computing, Cancun, Mexico, May, 1998.

65. S. Tongsima, C. Chantrapornchai, and E. H.-M. Sha, ``Probabilistic Loop Scheduling Considering Communication Overhead," in Proc. 4th Workshop on Job Scheduling Strategies for Parallel Processing, with IEEE 12th International Parallel Processing Symposium & 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP), Orlando, Florida, April, 1998.

66. Y. Tian, E. H.-M. Sha, C. Chantrapornchai and P. M. Kogge, ``Optimizing Data Scheduling on Processor-In-Memory Arrays," in Proc. IEEE 12th International Parallel Processing Symposium & 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP), Orlando, Florida, April, 1998, pp. 57-61.

67. D. Surma and E. H.-M. Sha, ``Project-Based approach to teaching Microprocessors and their Applications," in American Society for Engineering Education 1998 Spring Conference, Detroit, Michigan, April, 1998, pp. 216-220.

68. K. Wang, T. Yu and E. H.-M. Sha, ``RCRS: A Framework for Loop Scheduling with Limited Number of Registers," in Proc. IEEE 8th Great Lakes Symposium on VLSI, Lafayette, Louisiana, February, 1998, pp. 386-391.

69. D. Surma, E. H.-M. Sha and P. M. Kogge, ``SCORE: An efficient technique to reduce congestion in Parallel Systems," in Proc. 10th ISCA International Conference on Parallel and Distributed Computing Systems, New Orleans, LA, October, 1997, pp. 198-203.

70. Y. Tian, E. H.-M. Sha, C. Chantrapornchai, and P. M. Kogge, ``Efficient Data Placement for Processor-In-Memory Array Processors," in Proc. 9th International Conference on Parallel and Distributed Computing and Systems, Washington, D.C., October, 1997, pp. 79-84.

71. S. Tongsima, E. H.-M. Sha, C. Chantrapornchai, and N. Passos, ``Efficient Loop Scheduling and Pipelining for Applications with Non-uniform Loops," in Proc. 9th International Conference on Parallel and Distributed Computing and Systems, Washington, D.C., October, 1997, pp. 363-368.

72. S. Tongsima, C. Chantrapornchai, E. H.-M. Sha and N. Passos, ``Probabilistic Rotation: Scheduling Graphs with Uncertain Execution Time," in Proc. 1997 International Conference on Parallel Processing, Bloomingdale, Illinois, August 1997, pp. 292-295.

73. C. Chantrapornchai, M. Sheliga, S. Tongsima and E. H.-M. Sha, ``Rapid System Design Framework for Fuzzy Applications,'' in Proc. IEEE 40th Midwest Symposium on Circuits and Systems, Sacramento, California, August, 1997.

74. D. Surma and E. H.-M. Sha, ``Efficient Communication Scheduling with Re-routing based on Collision Graphs," in Proc. 1997 Annual International Symposium on High Performance Computing Systems, Winnipeg, Manitoba, Canada, July 10-12, 1997, pp. 483-492.

75. M. Sheliga, E. H.-M. Sha and P. Kogge, ``Hardware/Software Codesign for Video Compression Using the EXECUBE Processor Array," in Proc. 1997 IEEE National Aerospace and Electronics Conference, Dayton, Ohio, July, 1997.

76. C. Chantrapornchai, S. Tongsima and E. H.-M. Sha, ``Imprecise Task Schedule Optimization," in Proc. the Sixth IEEE International Conference on Fuzzy Systems, Barcelona, Spain, July, 1997, Vol. 3, pp. 1265-1270.

77. T. Yu, N. Passos, E. H.-M. Sha and R. D.-C. Ju, ``Algorithms and Hardware Support for Branch Anticipation," in Proc. IEEE Great Lakes Symposium on VLSI, Urbana, Illinois, March 1997, pp. 163-168.

78. S. Tongsima, C. Chantrapornchai, E. H.-M. Sha and N. Passos, ``Scheduling with Confidence for Probabilistic Data Flow Graphs," in Proc. IEEE Great Lakes Symposium on VLSI, Urbana, Illinois, March 1997, pp. 150-155.

79. D. Surma and E. H.-M. Sha, `` Hybrid Static-Dynamic Communication Scheduling for Parallel Systems," in Proc. 1997 ACM Symposium on Applied Computing, San Jose, California, February, 1997, pp. 374-379.

80. S. Tongsima, C, Chantrapornchai, E. H.-M. Sha and N. Passos, ``SHARP: Efficient Loop Scheduling with Data Hazard Reduction on Multiple Pipeline DSP Systems," in Proc. 1996 IEEE Workshop on VLSI Signal Processing, San Francisco, California, November, 1996, pp. 253-262.

81. P. M. Kogge, S. C. Bass, J. B. Brockman, D. Z. Chen and E. H.-M. Sha, ``Pursuing a Petaflop: Point Designs for 100TF Computers Using PIM Technologies," Sixth International Symposium on Frontiers of Massively Parallel Computations, Annapolis, Maryland, October, 1996.

82. N. Passos and E. H.-M. Sha, ``VHDL Synthesis of Multi-Dimensional Applications: a New Approach," in Proc. 1996 IEEE International Conference on Computer Designs, Austin, Texas, October, 1996, pp. 530-535.

83. C. Lang, N. Passos and E. H.-M. Sha, ``Polynomial-time Nested Loop Fusion with Full Parallelism," in Proc. 1996 International Conference on Parallel Processing, August, 1996, Vol 3, pp. 9-16.

84. D. Surma and E. H.-M. Sha, ``Static Communication Scheduling for Minimizing Collisions in Application Specific Parallel Systems," in Proc. 1996 International Conference on Application-specific Systems, Architectures and Processors, Chicago, Illinois, August, 1996, pp. 240-249.

85. M. Sheliga and E. H.-M. Sha, ``Hardware/Software Co-design for DSP Applications via the HMS Framework," in Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, Atlanta, Georgia, May, 1996, Vol. 2, pp. 1248-1251.

86. D. Surma, S. Tongsima and E. H.-M. Sha, ``Optimal Communication Scheduling Based on Collision Graph Model," in Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, Atlanta, Georgia, May, 1996, Vol. 6, pp. 3319-3322.

87. C. Chantrapornchai, S. Tongsima and E. H.-M. Sha, ``Minimization of Fuzzy Systems based on Fuzzy Inference Graph," in Proc. IEEE International Symposium on Circuits and Systems, Atlanta, Georgia, May, 1996, Vol. 4, pp. 651-654.

88. C. Chantrapornchai, S. Tongsima and E. H.-M. Sha, ``Rapid Prototyping for Fuzzy Systems," in Proc. IEEE Great Lakes Symposium on VLSI, Ames, Iowa, March, 1996, pp. 234-239.

89. N. Passos and E. H.-M. Sha, ``A Parameterized Index-Generator for the Multi-Dimensional Interleaving Optimization," in Proc. IEEE Great Lakes Symposium on VLSI, Ames, Iowa, March 1996, pp. 66-71.

90. M. Sheliga, N. Passos and E. H.-M. Sha, ``Fully Parallel Hardware/Software Codesign for Multi-Dimensional DSP Applications," in Proc. 4th IEEE International Workshop on Hardware/Software Co-design, Pittsburgh, Pennsylvania, March, 1996, pp. 18-25.

91. Q. Wang, N. Passos and E. H.-M. Sha, ``Multi-level Partitioning and Scheduling under Local Memory Constraint," (long paper) in Proc. IEEE Symposium on Parallel and Distributed Processing, San Antonio, Texas, December, 1995, pp. 612-619.

92. N. Passos and E. H.-M. Sha, ``Push-Up Scheduling: Optimal Polynomial-Time Resource Constrained Scheduling for Multi-Dimensional Applications," in Proc. IEEE/ACM International Conference on Computer-Aided Design, San Jose, California, November, 1995, pp. 588-591.

93. N. Passos, E. H.-M. Sha and L.-F. Chao, ``Fully Parallel Synchronous Circuit Design using Multi-Dimensional Interleaving," in Proc. IEEE International Conference on Computer Design, Austin, Texas, October, 1995, pp 440-445.

94. N. M. Sabine and E. H.-M. Sha, ``Integrating Selective Fault-Tolerance into Hard Real-Time Multiprocessor Schedules," in Proc. IEEE International Conference on Parallel and Distributed Computing Systems, Orlando, Florida, September, 1995, pp. 89-94.

95. D. R. Surma and E. H.-M. Sha, ``Application-Specific Communication Scheduling on Parallel Systems," in Proc. IEEE International Conference on Parallel and Distributed Computing Systems, Orlando, Florida, September, 1995, pp. 137-139.

96. S. Tongsima, N. Passos and E. H.-M. Sha, ``Architecture-Dependent Loop Scheduling via Communication-Sensitive Remapping," in Proc. International Conference on Parallel Processing, Wisconsin, August, 1995, pp. 97-104.

97. N. Passos, E. H.-M. Sha and L.-F. Chao, ``Memory-Efficient Fully Parallel Loop Transformation," in Proc. International Conference on Parallel Processing, Wisconsin, August, 1995, pp. 182-185.

98. N. Passos and E. H.-M. Sha, ``Memory/Time Optimization of 2-D Filters," in Proc. IEEE International Conference on Acoustics, Speech and Signal Processing, Detroit, Michigan, May, 1995, vol. 5, pp. 3223-3226.

99. L.-F. Chao and E. H.-M. Sha, ``Rate-Optimal Scheduling for Cycle-Static and Periodic Schedules," in Proc. IEEE International Conference on Acoustics, Speech and Signal Processing, Detroit, Michigan, May, 1995, vol. 5, pp. 3231-3234.

100. N. Passos, E. H.-M. Sha and L.-F. Chao, ``Optimizing Synchronous Systems for Multi-dimensional Applications," in Proc. IEEE European Design and Test Conference, Paris, France, March, 1995, pp 54-58.

101. H. Zhao, N. M. Sabine and E. H.-M. Sha, ``Improving Self-Timed Pipeline Ring Performance Through The Addition of Buffer Loops," in Proc. IEEE Great Lakes Symposium on VLSI, March, 1995, pp 218-223.

102. M. Sheliga and E. H.-M. Sha, ``Bus Minimization and Scheduling of Multi-Chip Modules," in Proc. IEEE Great Lakes Symposium on VLSI, Buffalo, New York, March, 1995, pp 40-45.

103. S. Tongsima, N. Passos and E. H.-M. Sha, ``Communication Sensitive Rotation Scheduling," in Proc. 1994 IEEE International Conference on Computer Design, Cambridge, Massachusetts, October, 1994, pp 150-153.

104. N. Passos and E. H.-M. Sha, ``Full Parallelism of Uniform Nested Loops by Multi-Dimensional Retiming," in Proc. 1994 International Conference on Parallel Processing, vol. 2, St. Charles, Illinois, August, 1994, pp. 130-133.

105. N. Passos, E. H.-M. Sha and S. C. Bass, ``Loop Pipelining for Scheduling Multi-dimensional Systems via Rotation," in Proc. IEEE/ACM 1994 Design Automation Conference (nominated for the Best Paper Award, 13 nominated out of 439 papers), San Diego, California, June, 1994, pp. 485-490.

106. L.-F. Chao and E. H.-M. Sha, `` Retiming and Clock Skew for Synchronous Systems," in Proc. IEEE 1994 International Symposium on Circuits and Systems, London, England, May, 1994, vol. 1, pp. 283-286.

107. N. Passos, E. H.-M. Sha and S. C. Bass, `` Partitioning and Retiming of Multi-dimensional Systems," in Proc. IEEE 1994 International Symposium on Circuits and Systems, London, England, May, 1994, vol. 4, pp. 227-230.

108. M. Sheliga and E. H.-M. Sha, ``Global Node Reduction of Linear Systems Using Ratio Analysis," in Proc. IEEE Seventh International Symposium on High-Level Synthesis, Niagara-on-the-Lake, Canada, May, 1994, pp. 140-145.

109. N. Passos, E. H.-M. Sha and S. C. Bass, ``Schedule-Based Multi-Dimensional Retiming on Data-Flow Graphs," in Proc. 1994 International Parallel Processing Symposium, Cancun, Mexico, April, 1994, pp. 195-199.

110. L.-F. Chao and E. H.-M. Sha, ``Unified Static Scheduling on Various Models," in Proc. 1993 International Conference on Parallel Processing, St. Charles, Illinois, August, 1993, pp. II 231-235.

111. L.-F. Chao, A. LaPaugh and E. H.-M. Sha, `` Rotation Scheduling: A Loop Pipelining Algorithm,'' in Proc. 30th ACM/IEEE Design Automation Conference, (nominated for the Best Paper Award), Dallas, Texas, June, 1993, pp. 566-572.

112. L.-F. Chao and E. H.-M. Sha, ``Efficient Retiming and Unfolding," in Proc. 1993 IEEE Int'l Conf. on Acoustic, Speech, and Signal Processing, Minneapolis, Minnesota, April, 1993, pp. I421-I424.

113. L.-F. Chao and E. H.-M. Sha, ``Static Scheduling of Uniform Nested Loops," in Proc. 7th International Parallel Processing Symposium, Newport Beach, California, April, 1993, pp.254-258.

114. K. Steiglitz and E. H.-M. Sha, ``Maintaining Bipartite Matchings in the Presence of Failures,'' in Proc. of 7th International Parallel Processing Symposium, (Long Paper), Newport Beach, California, April, 1993, pp. 57-64.

115. L.-F. Chao and E. H.-M. Sha, ``Rate-Optimal Static Scheduling for DSP Data-Flow Programs", in Proc. IEEE Third Great Lakes Symposium on VLSI, March 1993, pp 80-84.

116. L.F. Chao, E. H.-M. Sha and A. LaPaugh, ``Scheduling Cyclic Data-Flow Graphs by Retiming with Resource Constraints," in Proc. ACM/IEEE Sixth International Workshop on High-Level Synthesis, Dana Point, California, November, 1992, pp. 111-134.

117. L.-F. Chao and E. H.-M. Sha, ``Retiming and Unfolding Data-Flow Graphs," in Proc. 1992 International Conference on Parallel Processing, St. Charles, Illinois, August, 1992, pp. II 33-40.

118. L.-F. Chao and E. H.-M. Sha, ``Algorithms for Min-Cut Linear Arrangements of Outerplanar graphs" in Proc. 1992 IEEE Int'l Symposium on Circuits and Systems, San Diego, California, May, 1992, pp. 1851-1854.

119. K. Steiglitz and E. H.-M. Sha, ``An Error-Detectable Array for All-Substring Comparison," in Proc. 1992 IEEE Int'l Symposium on Circuits and Systems, San Diego, California, May, 1992, pp. 2941-2944.

120. L.-F. Chao and E. H.-M. Sha, ``Efficient Distributed Reconfiguration for Binary Trees on Diogenes Model," in Proc. 1992 Int'l Phoenix Conf. on Computers and Communications, Scottsdale, Arizona, April, 1992, pp. 464-471.

121. K. Steiglitz and E. H.-M. Sha, ``Run-Time Error Detection in Arrays Based on the Data-Dependency Graph," in Proc. 1992 IEEE Int'l Conf. on Acoustic, Speech, and Signal Processing, San. Francisco, March, 1992, Vol. 5, pp. 625-628.

122. L.-F. Chao and E. H.-M. Sha, ``Unfolding and Retiming Data-Flow DSP Programs for RISC Multiprocessor Scheduling," in Proc. 1992 IEEE Int'l Conf. on Acoustic, Speech, and Signal Processing, San Francisco, California, March, 1992, Vol. 5, pp. 565-568.

123. L.-F. Chao and E. H.-M. Sha, ``Optimizing Synchronous Systems via Retiming and Unfolding," in Proc. 1992 Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, March, 1992.

124. K. Steiglitz and E. H.-M. Sha, ``Explicit Constructions for Reliable Reconfigurable Array Architectures,'' in Proc. Third IEEE Symposium on Parallel and Distributed Processing, Dallas, Texas, December, 1991, pp. 640-647.

125. E. H.-M. Sha and L.-F. Chao, ``Design for Easily Applying Test Vectors to Improve Delay Fault Coverage,'' in Proc. 1991 IEEE Int'l Conf. on Computer-Aided Design, Santa Clara, California, November, 1991, pp. 500-503.

126. L.-F. Chao and E. H.-M. Sha, ``Planar Linear Arrangements for Outerplanar graphs," in Proc. 1991 Second Great Lakes Computer Science Conference, Kalamazoo, Michigan, October, 1991.

127. K. Steiglitz and E. H.-M. Sha, ``Reconfigurability and Reliability of Systolic/Wavefront Arrays,'' in Proc. 1991 IEEE Int'l Conf. on Acoustic, Speech, and Signal Processing, Toronto, Canada, May 1991, Vol. 2, pp. 1001-1004.

References:

Available upon request.