People > Edwin H-M Sha

Resume:

View the resume here.

Role in the Embedded Software Center:

Dr. Sha is a member of the implementation Group of the Embedded Software Center. He participates in the framework of this group.

Research Interests:

Dr.Sha's research interests include DSP architectures, Embedded systems, Parallel processing, Parallel architectures, High-level synthesis in VLSI, Fault-tolerant computing, CAD for application-specific systems, VLSI architectures, Software tools for parallel, distributed and embedded systems.

Selected Publications:

Recent Journal Paper List

1. ``Communication Reduction in Multiple Multicasts based on Hybrid Static-Dynamic Scheduling,"
   (with D. R. Surma and P. M. Kogge) Accepted for publication in IEEE Transactions on Parallel and Distributed Systems.
   
   
2. ``Optimizing Overall Loop Schedules using Prefetching and Partitioning,''
   (with F. Chen, and T. W. O'Neil) Accepted for publication in
   IEEE Transactions on Parallel and Distributed Systems.
   
   
3. ``Efficient Acceptable Design Exploration Based on Module Utility Selection,"
   (with C. Chantrapornchai, and X. Sharon Hu) in
   IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 19, No. 1, Jan. 2000, pp. 19-29 .
   
   
4. ``Probabilistic Loop Scheduling for Applications with Uncertain Execution Time,"
   (with S. Tongsima, C. Chantrapornchai, D. Surma and N. Passos) in
   IEEE Transactions on Computers, Vol. 49, No. 1, Jan. 2000, pp. 65-80.
   
   
5. ``Properties and Algorithms for Unfolding of Probabilistic Data-flow Graphs,"
   (with S. Tongsima, T. W. O'Neil, and C. Chantrapornchai) Accepted for publication in
   Journal of VLSI Signal Processing.
   
   
6. ``Efficient Module Selections for Finding Highly Acceptable Designs based on Inclusion Scheduling,''
   (with C. Chantrapornchai, and X. S. Hu) Accepted for publication in
   Journal of Systems Architecture.
   
   
7. ``Optimizing Page Replacement for Multiple-Level Memory Hierarchy,"
   (with C. Chantrapornchai) in
   International Journal of Computers and Their Applications Vol. 6, No. 4, Dec. 1999, pp. 212-222.
   
   
8. ``Scheduling of Uniform Multi-Dimensional Systems under Resource Constraints," (with N. Passos) in
   IEEE Transactions on VLSI Systems, Vol. 6, No. 4, December 1998, pp. 719-730.
   
   
9. ``Collision Graph based Communication Scheduling for Parallel Systems,"
   (with D. R. Surma) in
   International Journal of Computers and Their Applications. Vol. 5, No. 1, March 1998.
   
   
10. ``Rotation Scheduling: A Loop Pipelining Algorithm,"
    (with L.-F. Chao and A. LaPaugh) in
    IEEE Transactions on Computer Aided Design , Vol. 16, No. 3, March 1997, pp. 229-239.
    
    
11. ``Efficient Loop Scheduling and Pipelining for Applications with Non-uniform Loops,"
    (with S. Tongsima, C. Chantrapornchai, and N. Passos) in
    IASTED International Journal of Parallel and Distributed Systems and Networks, Vol. 1, No 4, 1998, pp. 204-211.
    
    
12. ``Reducing Data Hazards on Multi-pipelined DSP Architecture with Loop Scheduling,"
    (with S. Tongsima, C. Chantrapornchai and N. Passos) in
    Journal of VLSI Signal Processing, Vol. 18, 1998, pp. 111-123.
    
    
13. ``Communication Sensitive Loop Scheduling for DSP Applications,"
    (with S. Tongsima and N. Passos), (regular paper),
    IEEE Transactions on Signal Processing Vol. 45, No. 5, May 1997, pp. 1309-1322.
    
    
14. ``Multi-Dimensional Interleaving for Synchronous Circuit Design Optimization,"
    (with N. Passos and L.-F. Chao), (regular paper),
    {\it IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, Vol. 16, No. 2, February 1997, pp. 146-159.
    
    
15. ``Minimization of Memory Access Overhead for Multi-dimensional DSP Applications via Multi-level Partitioning and Scheduling,"
    (with Q. Wang and N. Passos), Accepted for publication (regular paper),
    IEEE Transactions on Circuits and Systems II. Vol. 44, No. 9, September 1997, pp. 741-753.
    
    
16. ``Hardware/Software Co-design With the HMS Framework,"
    (with M. Sheliga) (regular paper), in
    Journal of VLSI Signal Processing Systems, Vol. 13, No. 1, August 1996, pp. 37-56.
    
    
17. ``Achieving Full Parallelism using Multi-Dimensional Retiming,"
    (with N. Passos) (regular paper),
    IEEE Transactions on Parallel and Distributed Systems, Vol. 7, No. 11, November 1996, pp. 1150-1163.
    
    
18. ``Synchronous Circuit Optimization via Multi-Dimensional Retiming," (Part 1)
    (Part 2)
    (with N. Passos), (regular paper), in
    IEEE Transactions on Circuits and Systems, vol II - Analog and Signal Processing, Vol. 43, No. 7, July 1996, pp. 507-519.
    
    
19. ``Optimizing DSP Flow Graphs via Schedule-Based Multi-Dimensional Retiming,"
    (with N. Passos and S. C. Bass),
    IEEE Transactions on Signal Processing}, Vol. 44, No. 1, January, 1996, pp. 150-156.
    
    
20. ``Optimal Data Scheduling for Uniform Multi-dimensional Applications,"
    (with Q. Wang, and N. Passos)
    IEEE Transactions on Computers, Vol. 45, No. 12, December 1996, pp. 1439-1444.
    
    
21. ``Static Scheduling for Synthesis of DSP Algorithms on Various Models,"
    (with L.-F. Chao), (regular paper)
    Journal of VLSI Signal Processing, Vol 10, pp 207-223, 1995.
    
    
22. ``Scheduling Data-Flow Graphs via Retiming and Unfolding,"
    (with L.F. Chao) in (regular paper)
    IEEE Transactions on Parallel and Distributed Systems Vol. 8, No. 12, December 1997, pp. 1259-1267.
    
    
23. ``Maintaining Bipartite Matchings in the Presence of Failures,''
    (with K. Steiglitz), (regular paper)
    Networks} Journal, Vol. 23, no. 5, Aug. 1993, pp. 459-471.
    
    
24. ``Reconfigurability and Reliability of Systolic/Wavefront Arrays,''
    (with K. Steiglitz), (regular paper)
    IEEE Transactions on Computers, vol. 42, no. 7, July, 1993, pp. 854-862.
    
    
25. ``Error Detection in Arrays via Dependency Graphs,''
    (with K. Steiglitz), (regular paper)
    Journal of VLSI Signal Processing, vol. 4, no. 4, October 1992, pp 331-342.
    
    
26. Z. Yu, E. H.-M. Sha, N. Passos and R. Ju, ``Algorithms and Architecture Support for Pipelining and Scheduling Nested Loopw with Conditions," submitted to IEEE Transactions on Computers.
    
    
27. T. W. O'Neil, S. Tongsima, and E. H.-M. Sha, ``Extended Retiming: A Graph Transformation Technique for Optimal Scheduling of Data-Flow Graphs," submitted to IEEE Transactions on Parallel and Distributed Systems.
    
    
28. F. Chen, T. W. O'Neil, and E. H.-M. Sha, ``Optimizing Overall Loop Schedules using Prefetching and Partitioning,'' submitted to IEEE Transactions on Parallel and Distributed Systems.
    
    
29. ``A Fully Parallel Design Methodology for Multi-Dimensional DSP Applications," (with M. Sheliga and N. Passos) submitted to
    Journal of VLSI Signal Processing.
    
    
30. ``Efficient Polynomial-Time Nested Loop Fusion with Full Parallelism," (with N. Passos and T. O'Neil) submitted to
    IEEE Transactions on Parallel and Distributed Systems .
    
    
31. "Rapid Prototyping Implementation and Optimization based on Conceptual Specification for Fuzzy Applications," (with C. Chantrapornchai, M. Sheliga and S. Tongsima) submitted to to Journal of Fuzzy Sets and Systems.
    
    
32. D. Surma, E. H.-M. Sha and N. Passos, ``Communication Scheduling with Re-routing based on Static and Hybrid Techniques," submitted to Journal of Circuits, Systems and Computers.

1. Z. Wang, M. Kirkpatrick, and E. H.-M. Sha, ``Optimal Two Level Partitioning and Loop Scheduling for Hiding Memory Latency for DSP Applications,"
   in Proc. ACM 37th Design Automation Conference , Los Angeles, California, June, 2000
   
   
2. J. Ding, J. C. Furgeson and Edwin H..-M. Sha, ``Application Specific Image Compression for Virtual Conferencing,"
   in Proc. IEEE International Conference on Information Technology: Coding and Computing, Las Vegas, Nevada, March 2000.
   
   
3. J. Ding, M. Kirkpatrick, and E. H.-M. Sha, ``QoS Measures and Implementations Based on Various Models for Real-time Communications,"
   in Proc. 3rd IEEE Symposium on Application-Specific Systems and Software Engineering Technology, Richardson, Texas, March, 2000.
   
   
4. C. Chantrapornchai, E. H.-M. Sha and S. X. Hu, ``Efficient Algorithms for Acceptable Design Exploration," in Proc. IEEE Tenth Great Lakes Symposium on VLSI, Evanston, Illinois, March, 2000.
   
   
5. V. Andronache, E. H.-M. Sha and N. Passos, ``Design and Analysis of Efficient Application-Specific On-line Page Replacement Techniques,"
   in Proc. IEEE Tenth Great Lakes Symposium on VLSI, Evanston, Illinois, March, 2000.
   
   
6. T. W. O'Neil, and Edwin H.-M. Sha, ``Rate-Optimal Graph Transformation Based on Extended Retiming and Unfolding,"
   in Proc. 11th IASTED International Conference on Parallel and Distributed Computing and Systems, Cambridge, MA, November 1999.
   
   
7. Z. Wang, V. Andronache, and Edwin H.-M. Sha , ``Optimal Partitioning under Memory Constraints for Minimizing Average Schedule Length,"
   in Proc. 11th IASTED International Conference on Parallel and Distributed Computing and Systems, Cambridge, MA, November 1999.
   
   
8. F. Chen, and E. H.-M. Sha, ``Loop Scheduling and Partitions for Hiding Memory Latencies,"
   in Proc. IEEE 12th International Symposium on System Synthesis}, San Jose, CA, November 1999.
   
   
9. T. O'Neil, S. Tongsima, and E. H.-M. Sha, ``Optimal Scheduling of Data-Flow Graphs Using Extended Retiming,"
   in Proc. ISCA 12th International Conference on Parallel and Distributed Computing Systems, Fort Lauderdale, Florida, August, 1999.
   
   
10. N. L. Passos, R. Light, V. Andronache, E. H.-M. Sha, ``Design of 2-D Filters using a Parallel Processor Architecture,"
    in Proc. ISCA 12th International Conference on Parallel and Distributed Computing Systems, Fort Lauderdale, Florida, August, 1999.
    
    
11. T. O'Neil, S. Tongsima, and and E. H.-M. Sha, ``Extended Retiming: Optimal Scheduling via a Graph-Theoretical Approach,"
    in Proc. 1999 IEEE International Conference On Acoustics, Speech, and Signal Processing, Phoenix, Arizona, March 1999, Vol. 4, pp. 2001-2004.
    
    
12. S. Tongsima, T. O'Neil, and E. H.-M. Sha, ``Unfolding Probabilistic Data-flow Graphs Under Different Timing Models,"
    in Proc. 1999 IEEE International Conference On Acoustics, Speech, and Signal Processing, Phoenix, Arizona, March 1999, Vol 4, pp. 1889-1892.
    
    
13. T. Zhou, X. S. Hu and Edwin H.-M. Sha, ``A Probabilistic Performance Metric for Real-Time System Design ,"
    in Proc. 1999 7th International Workshop on Hardware Software Co-Design, Rome, Italy, May 1999, pp. 90-94.
    
    
14. T. Zhou, X. S. Hu and Edwin H.-M. Sha, ``Probabilistic Performance Estimation for Real-time Embedded Systems,"
    in Proc. 1999 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, March, 1999, pp. 83-88.
    
    
15. C. Chantrapornchai, E. H.-M. Sha, and X. S. Hu, ``Efficient Algorithms for Finding Highly Acceptable Designs Based on Module-Utility Selections,"
    in Proc. IEEE 9th Great Lakes Symposium on VLSI, Ann Arbor, Michigan, March, 1999, pp. 128-131.
    
    
16. Y. Tian, E. H.-M. Sha, C. Chantrapornchai, and P. M. Kogge, ``Efficient Data Placement and Replacement Algorithms for Multiple-Level Memory Hierarchy,"
    in Proc. 10th International Conference on Parallel and Distributed Computing and Systems, Las Vegas, Nevada, October, 1998, pp. 196-201.
    
    
17. F. Chen, S. Tongsima, and E. H.-M. Sha, ``Loop Scheduling Optimization with Data Prefetching based on Multi-dimensional Retiming,"
    in Porc. ISCA 11th International Conference on Parallel and Distributed Computing Systems, Chicago, Illinois, pp. 129-134.
    
    
18. F. Chen, S. Tongsima, and E. H.-M. Sha, ``Loop Scheduling Algorithm for Timing and Memory Operation Minimization with Register Constraint,''
    in Proc. 1998 IEEE Workshop on SIGNAL PROCESSING SYSTEMS (SiPS), Boston, Massachusetts, October, 1998.
    
    
19. C. Chantrapornchai, E. H.-M. Sha and S. X. Hu, ``Efficient Scheduling for Imprecise Timing Based on Fuzzy Theory,"
    in Proc. 1998 Midwest Symposium on Circuit and Systems, Notre Dame, Indiana, August, 1998.
    
    
20. Andrea Leonardi, Nelson L. Passos, and Edwin H.-M. Sha, ``Nested Loops Optimization for Multiprocessor Architecture Design",
    in Proc. 1998 Midwest Symposium on Circuit and Systems,i Notre Dame, Indiana, August, 1998.
    
    
21. S. Tongsima, C. Chantrapornchai, E. H.-M. Sha and N. Passos `` Optimizing Circuits with Confidence Probability using Probabilistic Retiming,"
    in Proc. IEEE International Conference on Circuits and Systems, Monterey, California, June, 1998
    
    
22. D. R. Surma, E. H.-M. Sha and P. M. Kogge, ``Compile-time Priority Assignment and Re-routing for Communication Minimization in Parallel Systems,"
    in Proc. IEEE International Conference on Circuits and Systems, Monterey, California, June, 1998
    
    
23. M. Sheliga, T. Yu, F. Chen, and E. H.-M. Sha, ``Graph Transformation for Communicaton Minimization Using Retiming,"
    in Proc. IEEE International Conference on Circuits and Systems, Monterey, California, June, 1998
    
    
24. T. Z. Yu, F. Chen and E. H.-M. Sha, ``Loop Scheduling Algorithms for Power Reduction,"
    in Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, Seattle, Washington, May 1998.
    
    
25. C. Chantrapornchai, S. Tongsima, E. H.-M. Sha and S. X. Hu, ``Dealing with Impreciseness in Architectural Synthesis,"
    in Proc. IASTED International Conference on Artificial Intelligence and Soft Computing, Cancun, Mexico, May, 1998.
    
    
26. Y. Tian, E. H.-M. Sha, C. Chantrapornchai and P. M. Kogge, ``Optimizing Data Scheduling on Processor-In-Memory Arrays,"
    in Proc. IEEE 12th International Parallel Processing Symposium & 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP), Orlando, Florida, April, 1998.
    
    
27. S. Tongsima, C. Chantrapornchai, and E. H.-M. Sha, ``Probabilistic Loop Scheduling Considering Communication Overhead,"
    in Proc. 4th Workshop on Job Scheduling Strategies for Parallel Processing, with IEEE 12th International Parallel Processing Symposium & 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP), Orlando, Florida, April, 1998.
    
    
28. D. Surma and E. H.-M. Sha, ``Project-Based approach to teaching Microprocessors and their Applications,"
    in American Society for Engineering Education 1998 Spring Conference, Detroit, Michigan, April, 1998.
    
    
29. K. Wang, T. Yu and E. H.-M. Sha, ``RCRS: A Framework for Loop Scheduling with Limited Number of Registers,"
    in Proc. IEEE 8th Great Lakes Symposium on VLSI, Lafayette, Louisiana, February, 1998.
    
    
30. ``SCORE: An efficient technique to reduce congestion in Parallel Systems,"
    (with D. Surma and P. M. Kogge) in 10th International Conference on Parallel and Distributed Computing Systems, New Orleans, LA, October, 1997.
    
    
31. ``Efficitent Data Placement for Processor-In-Memory Array Processors,"
    (with Y. Tian, C. Chantrapornchai, and P. M. Kogge) in Proc. 9th International Conference on Parallel and Distributed Computing and Systems, Washington, D.C., October, 1997.
    
    
32. ``Efficitent Loop Scheduling and Pipelining for Applications with Non-uniform Loops,"
    (with S. Tongsima, C. Chantrapornchai, and N. Passos) in Proc. 9th International Conference on Parallel and Distributed Computing and Systems, Washington, D.C., October, 1997.
    
    
33. ``Probabilistic Rotation: Scheduling Graphs with Uncertain Execution Time,"
    (with S. Tongsima, C. Chantrapornchai and N. Passos) in
    Proc. 1997 International Conference on Parallel Processing, Bloomingdale, Illinois, Aug., 1997.
    
    
34. ``Rapid System Design Framework for Fuzzy Applications''
    (with C. Chantrapornchai, M. Sheliga and S. Tongsima) in
    Proc. IEEE 40th Midwest Symposium on Circuits and Systems, Sacramento, California, August, 1997.
    
    
35. ``Efficient Communication Scheduling with Re-routing based on Collision Graphs,"
    (with D. Surma) in
    Proc. 1997 Annual International Symposium on High Performance Computing Systems, Winnipeg, Manitoba, Canada, July 10-12, 1997, pp. 483-492.
    
    
36. ``Hardware/Software Codesign for Video Compression Using the EXECUBE Processor Array,"
    (with M. Sheliga and P. Kogge) in
    Proc. 1997 IEEE National Aerospace and Electronics Conference, Dayton, Ohio, July, 1997.
    
    
37. ``Imprecise Task Schedule Optimization,"
    (with C. Chantrapornchai, and S. Tongsima) in
    Proc. the Sixth IEEE International Conference on Fuzzy Systems, Barcelona, Spain, July, 1997.
    
    
38. ``Hybrid Static-Dynamic Communication Scheduling for Parallel Systems"
    (with D. Surma) in
    Proc. 1997 ACM Symposium on Applied Computing, San Jose, California, Feb. 1997, pp. 374-379..
    
    
39. "Algorithms and Hardware Support for Branch Anticipation,"
    (with T. Yu, N. Passos and R. D.-C. Ju) in
    Proc. IEEE Great Lakes Symposium on VLSI, Urbana, Illinois, March 1997, pp. 163-168.
    
    
40. "Scheduling with Confidence for Probabilistic Data Flow Graphs,"
    (with S. Tongsima, C. Chantrapornchai, and N. Passos) in
    Proc. IEEE Great Lakes Symposium on VLSI, Urbana, Illinois, March 1997, pp. 150-155.
    
    
41. ``SHARP: Efficient Loop Scheduling with Data Hazard Reduction on Multiple Pipeline DSP Systems,"
    (with S. Tongsima, C, Chantrapornchai and N. Passos) in
    Proc. 1996 IEEE Workshop on VLSI Signal Processing, San Fransisco, California, November, 1996, pp. 253-262.
    
    
42. ``VHDL Synthesis of Multi-Dimensional Applications: a New Approach,"
    (with N. Passos) in
    Proc. 1996 IEEE International Conference on Computer Designs, Austin, Texas, October, 1996, pp. 530-535.
    
    
43. ``Polynomial-time Nested Loop Fusion with Full Parallelism,"
    (with C. Lang and N. Passos) (regular paper) in
    Proc. 1996 International Conference on Parallel Processing, August 1996, Vol 3, pp. 9-16.
    
    
44. ``Static Communication Scheduling for Minimizing Collisions in Application Specific Parallel Systems,"
    (with D. Surma) (regular paper) in
    Proc. 1996 International Conference on Application-specific Systems, Architectures and Processors, Chicago, Illinois, August 1996, pp. 240-249.
    
    
45. ``Hardware/Software Co-design for DSP Applications via the HMS Framework."
    (with Mike Sheliga) in
    Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, Atlanta, Georgia, May, 1996, Vol. 2, pp. 1248-1251.
    
    
46. ``Optimal Communication Scheduling Based on Collision Graph Model,"
    (with D. Surma and S. Tongsima) in
    Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, Atlanta, Georgia, May, 1996, Vol. 6, pp. 3319-3322.
    
    
47. ``Rapid Prototyping for Fuzzy Systems,"
    (with C. Chantrapornchai and S. Tongsima), in
    Proc. IEEE Great Lakes Symposium on VLSI, Ames, Iowa, March 1996 pp. 234-239.
    
    
48. ``A Parameterized Index-Generator for the Multi-Dimensional Interleaving Optimization,"
    (with N. Passos), in
    Proc. IEEE Great Lakes Symposium on VLSI, Ames, Iowa, March 1996, pp. 66-71.
    
    
49. ``Minimization of Fuzzy Systems based on Fuzzy Inference Graph,"
    (with C. Chantrapornchai and S. Tongsima) in
    Proc. IEEE International Symposium on Circuits and Systems, Atlanta, Georgia, 1996, Vol. 4, pp. 651-654.
    
    
50. ``Fully Parallel Hardware/Software Codesign for Multi-Dimensional DSP Applications,"
    (with M. Sheliga and N. Passos) in
    Proc. 4th IEEE International Workshop on Hardware/Software Co-design, Pittsburgh, Pennsylvania, March, 1996, pp. 18-25.
    
    
51. ``Push-Up Scheduling: Optimal Polynomial-Time Resource Constrained Scheduling for Multi-Dimensional Applications,"
    (with N. Passos) in
    Proc. IEEE/ACM International Conference on Computer-Aided Design, San Jose, California, November, 1995, pp. 588-591.
    
    
52. ``Multi-level Partitioning and Scheduling under Local Memory Constraint," < br> (with Q. Wang and N. Passos) in
    Proc. IEEE Symposium on Parallel and Distributed Processing, (long paper), San Antonio, Texas, Dec, 1995, pp. 612-619.
    
    
53. ``Fully Parallel Synchronous Circuit Design using Multi-Dimensional Interleaving,"
    (with N. Passos and L.-F. Chao) in
    Proc. IEEE Iinternational Conference on Computer Design, Austin, Texas, October, 1995, pp 440-445.
    
    
54. ``Integrating Selective Fault-Tolerance into Hard Real-Time Multiprocessor Schedules," (with N. M. Sabine) in
    Proc. IEEE International Conference on Parallel and Distributed Computing Systems, Orlando, Florida, September, 1995, pp. 89-94.
    
    
55. ``Application-Specific Communication Scheduling on Parallel Systems,"
    (with D. R. Surma) in
    Proc. IEEE International Conference on Parallel and Distributed Computing Systems, Orlando, Florida, September, 1995, pp. 137-139.
    
    
56. ``Architecture-Dependent Loop Scheduling via Communication-Sensitive Remapping,"
    (with S. Tongsima and N. Passos), in
    Proc. International Conference on Parallel Processing, Wisconsin, August, 1995, pp. 97-104.
    
    
57. ``Memory-Efficient Fully Parallel Loop Transformation,"
    (with N. Passos and L.-F. Chao), in
    Proc. International Conference on Parallel Processing, Wisconsin, August, 1995, pp. 182-185.
    
    
58. ``Optimizing Synchronous Systems for Multi-dimensional Applications,"
    (with N. Passos and L.-F. Chao), in
    Proc. IEEE European Design and Test Conference, Paris, France, March, 1995, pp 54-58.
    
    
59. ``Improving Self-Timed Pipeling Ring Performance Through The Addition of Buffer Loops,"
    (with Hai Zhao and N. M. Sabine), in
    Proc. IEEE Great Lakes Symposium on VLSI, March, 1995, pp 218-223 (regular paper).
    
    
60. ``Bus Minimization and Scheduling of Multi-Chip Modules,"
    (with M. Sheliga), in
    Proc. IEEE Great Lakes Symposium on VLSI, Buffalo, New York, March, 1995, pp 40-45 (regular paper).
    
    
61. ``Memory/Time Optimization of 2-D Filters,"
    (with N. Passos), in
    Proc. IEEE International Conference on Acoustics, Speech and Signal Processing, Detroit, Michigan, May, 1995, vol. 5, pp. 3223-3226.
    
    
62. ``Rate-Optimal Scheduling for Cyclo-Static and Periodic Schedules,"
    (with L.-F. Chao), in
    Proc. IEEE International Conference on Acoustics, Speech and Signal Processing, Detroit, Michigan, May, 1995, vol. 5, pp. 3231-3234.
    
    
63. ``Communication Sensitive Rotation Scheduling,"
    (with S. Tongsima and N. Passos) in
    Proc. 1994 IEEE International Conference on Computer Design, Cambridge, Massachusetts, October, 1994, pp 150-153.
    
    
64. ``Full Parallelism of Uniform Nested Loops by Multi-Dimensional Retiming,"
    (with N. Passos) in
    Proc. 1994 International Conference on Parallel Processing, vol. 2, St. Charles, Illinois, August, 1994, pp. 130-133.
    
    
65. ``Loop Pipelining for Scheduling Multi-dimensional Systems via Rotation,"
    (with N. Passos and S. C. Bass) in
    Proc. IEEE/ACM 1994 Design Automation Conference (nominated for the Best Paper Award, 13 nominated out of 439 papers), San Diego, California, June, 1994, pp. 485-490.
    
    
66. `` Retiming and Clock Skew for Synchronous Systems," (with L.-F. Chao) in
    Proc. IEEE 1994 Interenational Symposium on Circuits and Systems, London, England, May, 1994, vol. 1, pp. 283-286.
    
    
67. `` Partitioning and Retiming of Multi-dimensional Systems,"
    (with N. Passos and S. C. Bass) in
    Proc. IEEE 1994 Interenational Symposium on Circuits and Systems, London, England, May, 1994, vol. 4, pp. 227-230.
    
    
68. ``Global Node Reduction of Linear Systems Using Ratio Analysis,"
    (with M. Sheliga) in
    Proc. IEEE Seventh International Symposium on High-Level Synthesis, Niagara-on-the-Lake, Canada, May, 1994, pp. 140-145.
    
    
69. ``Schedule-Based Multi-Dimensional Retiming on Data-Flow Graphs,"
    (with N. Passos and S. C. Bass) in
    Proc. 1994 International Parallel Processing Symposium, Cancun, Mexico, April, 1994, pp. 195-199.
    
    
70. `` Rotation Scheduling: A Loop Pipelining Algorithm,'' (with L.-F. Chao and A. LaPaugh) in
    Proc. 30th ACM/IEEE Design Automation Conference, (nominated for the Best Paper Award), Dallas, Texas, June 1993, pp. 566-572.
    
    
71. ``Rate-Optimal Static Scheduling for DSP Data-Flow Programs", (with L.-F. Chao), in
    Proc. IEEE Third Great Lakes Symposium on VLSI, March 1993, pp 80-84.
    
    
72. ``Efficient Retiming and Unfolding," (with L.-F. Chao) in
    Proc. 1993 IEEE Int'l Conf. on Acoustic, Speech, and Signal Processing, Minneapolis, Minnesota, April, 1993, pp. I421-I424.
    
    
73. ``Static Scheduling of Uniform Nested Loops," (with L.-F. Chao), in
    Proc. 7th International Parallel Processing Symposium, Newport Beach, California, April, 1993, pp.254-258.
    
    
74. ``Maintaining Bipartite Matchings in the Presence of Failures,'' (with K. Steiglitz), in
    Proc. of 7th International Parallel Processing Symposium, (Long Paper), Newport Beach, California, April, 1993, pp. 57-64.
    
    
75. ``Unified Static Scheduling on Various Models," (with L.-F. Chao), in
    Proc. 1993 International Conference on Parallel Processing, St. Charles, Illinois, August 1993, pp. II 231-235.
    
    
76. ``Retiming and Unfolding Data-Flow Graphs," (with L.F. Chao),
    Proc. 1992 International Conference on Parallel Processing, St. Charles, Illinois, August 1992, pp. II 33-40.
    
    
77. ``Scheduling Cyclic Data-Flow Graphs by Retiming with Resource Constraints," (with L.F. Chao and A. LaPaugh),
    ACM/IEEE Sixth International Workshop on High-Level Synthesis, Dana Point, California, November 1992, pp. 111-134.
    
    
78. ``Algorithms for Min-Cut Linear Arrangements of Outerplanar graphs" (with L.F. Chao),
    Proc. 1992 IEEE Int'l Symposium on Circuits and Systems, San Diego, California, May 1992, pp. 1851-1854.
    
    
79. ``An Error-Detectable Array for All-Substring Comparison,"
    Proc. 1992 IEEE Int'l Symposium on Circuits and Systems, San Diego, California, May 1992, pp 2941-2944.
    
    
80. ``Run-Time Error Detection in Arrays Based on the Data-Dependency Graph," (with K. Steiglitz),
    Proc. 1992 IEEE Int'l Conf. on Acoustic, Speech, and Signal Processing, San. Francisco, March 1992, Vol. 5, pp. 625-628.
    
    
81. ``Unfolding and Retiming Data-Flow DSP Programs for RISC Multiprocessor Scheduling" (with L.F. Chao),
    Proc. 1992 IEEE Int'l Conf. on Acoustic, Speech, and Signal Processing, San Francisco, California, March 1992, Vol. 5, pp. 565-568.
    
    
82. ``Efficient Distributed Reconfiguration for Binary Trees on Diogenes Model," (with L.F. Chao),
    Proc. 1992 Int'l Phoenix Conf. on Computers and Communications, Scottsdale, Arizona, April 1992, pp. 464-471.
    
    
83. ``Optimizing Synchronous Systems via Retiming and Unfolding," (with L.F. Chao),
    Tau 1992: 1992 Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, March 1992.
    
    
84. ``Explicit Constructions for Reliable Reconfigurable Array Architectures,'' (with K. Steiglitz),
    Proc. Third IEEE Symposium on Parallel and Distributed Processing, Dallas, Texas, Dec. 1991, pp. 640-647
    
    
85. ``Planar Linear Arrangements for Outerplanar graphs," (with L.F. Chao),
    Proc. 1991 Second Great Lakes Computer Science Conference, Kalamazoo, Michigan, Oct. 1991.
    
    
86. ``Design for Easily Applying Test Vectors to Improve Delay Fault Coverage,'' (with L.F. Chao),
    Proc. 1991 IEEE Int'l Conf. on Computer-Aided Design, Santa Clara, California, Nov. 1991, pp. 500-503.
    
    
87. ``Reconfigurability and Reliability of Systolic/Wavefront Arrays,'' (with K. Steiglitz),
    Proc. 1991 IEEE Int'l Conf. on Acoustic, Speech, and Signal Processing, Toronto, Canada, May 1991, Vol. 2, pp. 1001-1004.